M16C63 Datasheet, PDF (70/115 Pages) Renesas Technology Corp – RENESAS MCU

M16C/63 Group
5. Electrical Characteristics
V_CC1 = V_CC2 = 5 V
Timing Requirements
(V_CC1 = V_CC2 = 5 V, V_SS = 0 V, at T_opr = -20 to 85°C/-40 to 85°C unless otherwise specified)
5.2.3 Timing Requirements (Memory Expansion Mode and Microprocessor
Mode)
Table 5.34 Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Unit
Min.
Max.
t_ac1(RD-DB)
Data input access time (for setting with no wait)
(Note 1)
ns
t_ac2(RD-DB)
Data input access time (for setting with 1 to 3 waits)
(Note 2)
ns
t_ac3(RD-DB)
Data input access time (when accessing multiplex bus area)
(Note 3)
ns
t_ac4(RD-DB)
Data input access time (for setting with 2φ + 3φ or more)
(Note 4)
ns
t_su(DB-RD)
t_su(RDY-BCLK)
Data input setup time
RDY input setup time
40
ns
30
ns
t_{su(HOLD-BCLK)}
HOLD input setup time
40
ns
t_h(RD-DB)
t_h(BCLK-RDY)
t_h(BCLK-HOLD)
Data input hold time
RDY input hold time
HOLD input hold time
0
ns
0
ns
0
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
0----.-5----×_{-----1---0----}⁹ _{– 45[ns]}
f_(BCLK)
2. Calculated according to the BCLK frequency as follows:
-⁽--ⁿ----+-----0---.--5---⁾----^×-----1---0---⁹- – 45[ns]
f_(BCLK)
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
3. Calculated according to the BCLK frequency as follows:
-⁽--ⁿ----–-----0---.-5----⁾---^×-----1---0---⁹- – 45[ns]
f_(BCLK)
n is 2 for 2 waits setting, and 3 for 3 waits setting.
4. Calculated according to the BCLK frequency as follows:
-ⁿ----^×-----1---0---⁹- – 45[ns]
f_(BCLK)
n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 70 of 113