M16C63 Datasheet, PDF (29/115 Pages) Renesas Technology Corp – RENESAS MCU

M16C/63 Group
4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
4.1 SFRs
An SFR is a control register for a peripheral function. Table 4.1 to Table 4.15 list SFR information.
Table 4.1 SFR Information (1/16) ⁽¹⁾
Address
0000h
0001h
0002h
0003h
Register
0004h Processor Mode Register 0
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Chip Select Control Register
External Area Recovery Cycle Control Register
Protect Register
Data Bank Register
Oscillation Stop Detection Register
Program 2 Area Control Register
External Area Wait Control Expansion Register
Peripheral Clock Select Register
Sub Clock Division Control Register
Clock Prescaler Reset Flag
Peripheral Clock Stop Register
Reset Source Determine Register
Voltage Detector 2 Flag Register
001Ah Voltage Detector Operation Enable Register
001Bh
001Ch
001Dh
001Eh
001Fh
Chip Select Expansion Control Register
Processor Mode Register 2
Symbol
Reset Value
PM0
PM1
CM0
CM1
CSR
EWR
PRCR
DBR
CM2
0000 0000b (CNVSS pin is low)
0000 0011b (CNVSS pin is high) ⁽²⁾
0000 1000b
0100 1000b
0010 0000b
01h
XXXX XX00b
00h
00h
0X00 0010b ⁽³⁾
PRG2C
EWC
PCLKR
SCM0
CPSRF
PCLKSTP1
RSTFR
VCR1
VCR2
CSE
XXXX XX00b
00h
0000 0011b
XXXX X000b
0XXX XXXXb
X000 0000b
XX00 001Xb (hardware reset) ⁽⁴⁾
0000 1000b ⁽²⁾
000X 0000b ^{(2, 5)}
001X 0000b ^{(2, 6)}
00h
PM2
XX00 0X01b
Notes:
1.
2.
3.
4.
5.
6.
X: Undefined
The blank areas are reserved. No access is allowed.
Software reset, watchdog timer reset, oscillator stop detect reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect the following
bits and registers: the VCR1 register, the VCR2 register, and bits PM01 and PM00 in the PM0 register.
Oscillator stop detect reset does not affect bits CM20, CM21, and CM27.
The state of bits in the RSTFR register depends on the reset type.
This is the reset value when the LVDAS bit of address OFS1 is 1 during hardware reset.
This is the reset value after voltage monitor 0 reset, power-on reset, and when the LVDAS bit of address OFS1 is 0 during hardware reset.
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
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