English
Language : 

M16C63 Datasheet, PDF (95/115 Pages) Renesas Technology Corp – RENESAS MCU
M16C/63 Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(in no wait state setting)
Read timing
BCLK
CSi
td(BCLK-CS)
30ns(max.)
tcyc
th(BCLK-CS)
0ns(min.)
VCC1 = VCC2 = 3 V
ADi
BHE
ALE
RD
DBi
Write timing
BCLK
CSi
td(BCLK-AD)
30ns(max.)
td(BCLK-ALE) th(BCLK-ALE)
25ns(max.)
-4ns(min.)
th(BCLK-AD)
0ns(min.)
th(RD-AD)
0ns(min.)
td(BCLK-RD)
30ns(max.)
th(BCLK-RD)
0ns(min.)
tac1(RD-DB)
(0.5 × tcyc -60)ns(max.)
Hi-Z
tsu(DB-RD)
50ns(min.)
th(RD-DB)
0ns(min.)
td(BCLK-CS)
30ns(max.)
tcyc
th(BCLK-CS)
0ns(min.)
ADi
BHE
ALE
WR, WRL,
WRH
DBi
td(BCLK-AD)
30ns(max.)
th(BCLK-AD)
0ns(min.)
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
-4ns(min.)
td(BCLK-WR)
30ns(max.)
th(WR-AD)
(0.5 × tcyc -10)ns(min.)
th(BCLK-WR)
0ns(min.)
Hi-Z
td(BCLK-DB)
40ns(max.)
th(BCLK-DB)
0ns(min.)
tcyc = 1
f(BCLK)
td(DB-WR)
th(WR-DB)
(0.5 × tcyc -40)ns(min.) (0.5 × tcyc -10)ns(min.)
Measuring conditions
y VCC1 = VCC2 = 3 V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.29 Timing Diagram
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 95 of 113