M16C63 Datasheet, PDF (23/115 Pages) Renesas Technology Corp – RENESAS MCU

M16C/63 Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a
register bank, and there are two register banks.
b31
R2
R3
b15
b8 b7
b0
R0H (high-order bits of R0) R0L (low-order bits of R0)
R1H (high-order bits of R1) R1L (low-order bits of R1)
R2
R3
A0
A1
FB
Data registers ⁽¹⁾
Address registers ⁽¹⁾
Frame base registers ⁽¹⁾
b19
b15
b0
INTBH
INTBL
INTBH is the 4 high-order bits of the INTB register and
INTBL is the 16 low-order bits.
b19
b0
PC
Interrupt table register
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
Flag register
b15
IPL
b8 b7
b0
U I OB S Z DC
Note:
1. These registers compose a register bank. There are two register banks.
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 2.1 CPU Registers
2.1 Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can
be split into high-order (R0H/R1H) and low-order (R0L/R1L) bits to be used separately as 8-bit data
registers.
R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers
R2R0 and R3R1, respectively.
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
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