M16C63 Datasheet, PDF (96/115 Pages) Renesas Technology Corp – RENESAS MCU

M16C/63 Group
5. Electrical Characteristics
V_CC1 = V_CC2 = 3 V
Switching Characteristics
(V_CC1 = V_CC2 = 3 V, V_SS = 0 V, at T_opr = -20 to 85°C/-40 to 85°C unless otherwise specified)
5.3.4.2 In 1 to 3 Waits Setting and When Accessing External Area
Table 5.57
Symbol
t_d(BCLK-AD)
t_h(BCLK-AD)
t_h(RD-AD)
t_h(WR-AD)
t_d(BCLK-CS)
t_h(BCLK-CS)
t_d(BCLK-ALE)
t_h(BCLK-ALE)
t_d(BCLK-RD)
t_h(BCLK-RD)
t_d(BCLK-WR)
t_h(BCLK-WR)
t_d(BCLK-DB)
t_h(BCLK-DB)
t_d(DB-WR)
t_h(WR-DB)
t_d(BCLK-HLDA)
Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When
Accessing External Area)
Parameter
Measuring
Condition
Standard
Min.
Max.
Unit
Address output delay time
30
ns
Address output hold time (in relation to BCLK)
0
ns
Address output hold time (in relation to RD)
0
ns
Address output hold time (in relation to WR)
(Note 2)
ns
Chip select output delay time
30
ns
Chip select output hold time (in relation to BCLK)
0
ns
ALE signal output delay time
25
ns
ALE signal output hold time
RD signal output delay time
RD signal output hold time
-4
ns
See
Figure 5.28
30
ns
0
ns
WR signal output delay time
30
ns
WR signal output hold time
0
ns
Data output delay time (in relation to BCLK)
40
ns
Data output hold time (in relation to BCLK) ⁽³⁾
0
ns
Data output delay time (in relation to WR)
(Note 1)
ns
Data output hold time (in relation to WR) ⁽³⁾
(Note 2)
ns
HLDA output delay time
40
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
(_---n_{----+-----0---.--5---})_----×_{----1---0----}⁹_{- – 40[ns]}
f_(BCLK)
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
When n = 1, f_(BCLK) is 12.5 MHz or less.
2. Calculated according to the BCLK frequency as follows:
0----.-5----×_{-----1---0----}⁹ _{– 10[ns]}
f_(BCLK)
3. This standard value shows the timing when the output is
off, and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-
up (pull-down) resistance value.
Hold time of data bus is expressed in
t=−CR × ln(1−V_OL/V_CC2)
by a circuit of the right figure.
For example, when V_OL = 0.2V_CC2, C = 30 pF, R = 1 kΩ,
hold time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2)
= 6.7 ns.
R
DBi
C
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 96 of 113