M16C63 Datasheet, PDF (80/115 Pages) Renesas Technology Corp – RENESAS MCU

M16C/63 Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(in wait state setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and
when accessing external area)
Read timing
t cyc
V_CC1 = V_CC2 = 5 V
BCLK
CSi
ADi
BHE
ALE
td(BCLK-CS)
25ns(max.)
td(BCLK-AD)
25ns(max.)
td(BCLK-ALE)
15ns(max.)
th(BCLK-ALE)
-4ns(min.)
RD
DBi
Hi-Z
Write timing
tcyc
td(BCLK-RD)
25ns(max.)
tac4(RD-DB)
(n × tcyc -45)ns(max.)
tsu(DB-RD)
40ns(min.)
th(BCLK-CS)
2ns(min.)
th(BCLK-AD)
2ns(min.)
th(RD-AD)
0ns(min.)
th(BCLK-RD)
0ns(min.)
th(RD-DB)
0ns(min.)
BCLK
td(BCLK-CS)
25ns(max.)
CSi
ADi
BHE
ALE
td(BCLK-AD)
25ns(max.)
td(BCLK-ALE)
15ns(max.)
th(BCLK-ALE)
-4ns(min.)
WR, WRL
WRH
DBi
Hi-Z
td(BCLK-WR)
25ns(max.)
td(BCLK-DB)
40ns(min.)
th(BCLK-CS)
2ns(min.)
th(BCLK-AD)
2ns(min.)
th(WR-AD)
(0.5 × tcyc-10)ns(min.)
th(BCLK-WR)
0ns(min.)
th(BCLK-DB)
2ns(min.)
1
tcyc = _f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 5 V
y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V
y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V
td(DB-WR)
{(n-0.5) × tcyc -40}ns(min.)
th(WR-DB)
(0.5 × tcyc -10)ns(min.)
n: 3 (when 2φ + 3φ)
4 (when 2φ + 4φ or 3φ + 4φ)
5 (when 4φ + 5φ)
Figure 5.18 Timing Diagram
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
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