M16C63 Datasheet, PDF (91/115 Pages) Renesas Technology Corp – RENESAS MCU

M16C/63 Group
5. Electrical Characteristics
V_CC1 = V_CC2 = 3 V
Timing Requirements
(V_CC1 = V_CC2 = 3 V, V_SS = 0 V, at T_opr = -20 to 85°C/-40 to 85°C unless otherwise specified)
5.3.3 Timing Requirements (Memory Expansion Mode and Microprocessor
Mode)
Table 5.55 Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Unit
Min.
Max.
t_ac1(RD-DB)
t_ac2(RD-DB)
t_ac3(RD-DB)
t_ac4(RD-DB)
t_su(DB-RD)
t_su(RDY-BCLK)
t_{su(HOLD-BCLK)}
t_h(RD-DB)
t_h(BCLK-RDY)
t_h(BCLK-HOLD)
Data input access time (for setting with no wait)
Data input access time (for setting with wait)
Data input access time (when accessing multiplex bus area)
Data input access time (for setting with 2 φ + 3 φ or more)
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
RDY input hold time
HOLD input hold time
(Note 1)
ns
(Note 2)
ns
(Note 3)
ns
(Note 4)
ns
50
ns
40
ns
50
ns
0
ns
0
ns
0
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
0----.-5----×_{-----1---0----}⁹ _{– 60[ns]}
f_(BCLK)
2. Calculated according to the BCLK frequency as follows:
-⁽--ⁿ----+-----0---.--5---⁾----^×-----1---0---⁹- – 60[ns] n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
f_(BCLK)
3. Calculated according to the BCLK frequency as follows:
-⁽--ⁿ----–-----0---.-5----⁾---^×-----1---0---⁹- – 60[ns] n is 2 for 2 waits setting, 3 for 3 waits setting.
f_(BCLK)
4. Calculated according to the BCLK frequency as follows:
-ⁿ----^×-----1---0---⁹- – 60[ns]
f_(BCLK)
n is 3 for 2 φ + 3 φ, 4 for 2 φ + 4 φ, 4 for 3 φ + 4 φ, 5 for 4 φ + 5 φ,.
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 91 of 113