R5F61655N50FPV Datasheet, PDF (94/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 2 CPU
2.8 Addressing Modes and Effective Address Calculation
The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a
subset of these addressing modes.
Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to
specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.12 Addressing Modes
No. Addressing Mode
Symbol
1 Register direct
Rn
2 Register indirect
@ERn
3 Register indirect with displacement
@(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn)
4 Index register indirect with displacement
@(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L)
@(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L)
5 Register indirect with post-increment
@ERn+
Register indirect with pre-decrement
@–ERn
Register indirect with pre-increment
@+ERn
Register indirect with post-decrement
@ERn–
6 Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
7 Immediate
#xx:3/#xx:4/#xx:8/#xx:16/#xx:32
8 Program-counter relative
@(d:8,PC)/@(d:16,PC)
9 Program-counter relative with index register @(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC)
10 Memory indirect
@@aa:8
11 Extended memory indirect
@@vec:7
2.8.1 Register Direct—Rn
The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the
register field in the instruction code.
R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers.
ER0 to ER7 can be specified as 32-bit registers.
Rev. 2.00 Oct. 20, 2009 Page 62 of 1340
REJ09B0499-0200