R5F61655N50FPV Datasheet, PDF (419/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 11 EXDMA Controller (EXDMAC)
11.3.8 Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7)
CLSBR0 to CLSBR7 are 32-bit readable/writable registers that store the transfer data. The transfer
data is stored in order from CLSBR0 to CLSBR7 in cluster transfer mode. The data stored in
cluster transfer mode or by the CPU write operation is held until the next cluster transfer or CPU
write operation is performed.
When reading the data stored in cluster transfer mode by the CPU, check the completion of cluster
transfer and then perform only a cluster-size read specified for the cluster transfer. Data with
another size is undefined.
In cluster transfer mode, the same CLSBR is used for all channels. When the CPU write operation
to CLSBR conflicts with cluster transfer, the contents of transferred data are not guaranteed. When
cluster transfer read/write address mode is specified and if another channel is set for cluster
transfer, the transferred data may be overwritten.
Bit
Bit Name
Initial Value
R/W
31
30
29
28
27
26
25
24
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial Value
R/W
23
22
21
20
19
18
17
16
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial Value
R/W
15
14
13
12
11
10
9
8
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 2.00 Oct. 20, 2009 Page 387 of 1340
REJ09B0499-0200