R5F61655N50FPV Datasheet, PDF (1335/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 29 Electrical Characteristics
Item
Symbol
WDT
SCI
Overflow output delay time t_WOVD
Input clock
cycle
Asynchronous t_Scyc
Clocked
synchronous
Input clock pulse width
t
SCKW
Input clock rise time
t
SCKr
Input clock fall time
t_SCKf
SCI
Transmit data delay time
t
TXD
Receive data setup time
t_RXS
(clocked synchronous)
Receive data hold time
t
RXH
(clocked synchronous)
A/D
Trigger input setup time
t
TRGS
converter
IIC2
SCL input cycle time
t
SCL
SCL input high pulse width t_SCLH
SCL input low pulse width t
SCLL
SCL, SDA input falling time t
Sf
SCL, SDA input spike pulse t
SP
removal time
SDA input bus free time
t
BUF
Start condition input hold time t_STAH
Repeated start condition input t_STAS
setup time
Stop condition input setup t
STOS
time
Data input setup time
t
SDAS
Data input hold time
t
SDAH
SCL, SDA capacitive load Cb
SCL, SDA falling time
t
Sf
Min.
⎯
4
6
Max.
40
⎯
⎯
0.4
0.6
⎯
1.5
⎯
1.5
⎯
40
40
⎯
40
⎯
30
⎯
12 t_CYC + ⎯
600
3 t_CYC + ⎯
300
5 t_CYC + ⎯
300
⎯
300
⎯
1t
CYC
5t
CYC
⎯
3 t_CYC
⎯
3 t_CYC
⎯
1 t_CYC + 20 ⎯
0
⎯
0
⎯
⎯
400
⎯
300
Unit
ns
t_cyc
Test Conditions
Figure 29.33
Figure 29.34
t
Scyc
t
cyc
t_cyc
ns Figure 29.35
ns
ns
ns Figure 29.36
ns Figure 29.37
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
Rev. 2.00 Oct. 20, 2009 Page 1303 of 1340
REJ09B0499-0200