R5F61655N50FPV Datasheet, PDF (610/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.1 TPU (Unit 0) Functions
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
Count clock
Pφ/1
Pφ/4
Pφ/16
Pφ/64
TCLKA
TCLKB
TCLKC
TCLKD
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
TCLKA
TCLKB
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/1024
TCLKA
TCLKB
TCLKC
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
Pφ/4096
TCLKA
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/1024
TCLKA
TCLKC
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
TCLKA
TCLKC
TCLKD
General registers
(TGR)
TGRA_0 TGRA_1 TGRA_2 TGRA_3 TGRA_4 TGRA_5
TGRB_0 TGRB_1 TGRB_2 TGRB_3 TGRB_4 TGRB_5
General registers/
TGRC_0 ⎯
⎯
TGRC_3 ⎯
⎯
buffer registers
TGRD_0
TGRD_3
I/O pins
⎯
⎯
⎯
TIOCA3 TIOCA4 TIOCA5
TIOCB3 TIOCB4 TIOCB5
TIOCC3
TIOCD3
Counter clear function TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
Compare 0 output ⎯
⎯
⎯
O
O
O
match
output
1 output ⎯
⎯
⎯
O
O
O
Toggle ⎯
⎯
⎯
O
O
O
output
Input capture function O
O
⎯
O
O
O
Synchronous
O
O
O
O
O
O
operation
PWM mode
O
O
O
O
O
O
Phase counting mode ⎯
O
O
⎯
O
O
Buffer operation
O
⎯
⎯
O
⎯
⎯
DTC activation
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
[Legend]
O: ^Possible
⎯: Not possible
Rev. 2.00 Oct. 20, 2009 Page 578 of 1340
REJ09B0499-0200