R5F61655N50FPV Datasheet, PDF (1027/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 21 A/D Converter
ADST
A/D conversion one-cycle execution
Set *
ADF
A/D conversion time
Channel 4 (AN4) _{Waiting for conversion A/D conversion 1}
operation state
Channel 5 (AN5)
operation state
Channel 6 (AN6)
operation state
Channel 7 (AN7)
operation state
ADDRE
Waiting for conversion
A/D conversion 2
Waiting for conversion
Transfer
A/D conversion 3
Waiting for conversion
A/D conversion result 1
Clear*
Waiting for conversion
Waiting for conversion
Waiting for conversion
ADDRF
ADDRG
A/D conversion result 2
A/D conversion result 3
ADDRH
Note: ↓ indicates the timing of instruction execution by software.
Figure 21.5 Example of A/D Conversion
(One-Cycle Scan Mode, Three Channels (AN4 to AN6) Selected)
Rev. 2.00 Oct. 20, 2009 Page 995 of 1340
REJ09B0499-0200