R5F61655N50FPV Datasheet, PDF (186/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 7 Interrupt Controller
7.6.4 Interrupt Response Times
Table 7.4 shows interrupt response times – the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The symbols for execution
states used in table 7.4 are explained in table 7.5.
This LSI is capable of fast word transfer to on-chip memory, so allocating the program area in on-
chip ROM and the stack area in on-chip RAM enables high-speed processing.
Table 7.4 Interrupt Response Times
Normal Mode*⁵
Advanced Mode
Maximum Mode*⁵
Execution State
Interrupt
Control
Mode 0
Interrupt
Control
Mode 2
Interrupt
Control
Mode 0
Interrupt
Control
Mode 2
Interrupt
Control
Mode 0
Interrupt
Control
Mode 2
Interrupt priority determination*¹
3
Number of states until executing
instruction ends*²
PC, CCR, EXR stacking
S_K to 2·S_K*⁶ 2·S_K
Vector fetch
Instruction fetch*³
Internal processing*⁴
1 to 19 + 2·S_I
S_K to 2·S_K*⁶ 2·S_K
S_h
2·S_I
2
2·S_K
2·S_K
Total (using on-chip memory) 10 to 31 11 to 31 10 to 31 11 to 31 11 to 31 11 to 31
Notes: 1. Two states for an internal interrupt.
2. In the case of the MULXS or DIVXS instruction
3. Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine.
4. Internal operation after interrupt acceptance or after vector fetch
5. Not available in this LSI.
6. When setting the SP value to 4n, the interrupt response time is S ; when setting to 4n +
K
2, the interrupt response time is 2·S .
K
Rev. 2.00 Oct. 20, 2009 Page 154 of 1340
REJ09B0499-0200