R5F61655N50FPV Datasheet, PDF (138/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 6 Exception Handling
6.2 Exception Sources and Exception Handling Vector Table
Different vector table address offsets are assigned to different exception sources. The vector table
addresses are calculated from the contents of the vector base register (VBR) and vector table
address offset of the vector number. The start address of the exception service routine is fetched
from the exception handling vector table indicated by this vector table address.
Table 6.2 shows the correspondence between the exception sources and vector table address
offsets. Table 6.3 shows the calculation method of exception handling vector table addresses.
Table 6.2 Exception Handling Vector Table
Exception Source
Reset
Reserved for system use
Illegal instruction
Trace
Reserved for system use
Interrupt (NMI)
Trap instruction (#0)
(#1)
(#2)
(#3)
CPU address error
DMA address error*³
UBC break interrupt
Reserved for system use
Sleep interrupt
Vector Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
⏐
17
18
Vector Table Address Offset*¹
Normal Mode*²
Advanced, Middle*²,
Maximum*² Modes
H'0000 to H'0001 H'0000 to H'0003
H'0002 to H'0003
H'0004 to H'0007
H'0004 to H'0005 H'0008 to H'000B
H'0006 to H'0007 H'000C to H'000F
H'0008 to H'0009
H'0010 to H'0013
H'000A to H'000B H'0014 to H'0017
H'000C to H'000D H'0018 to H'001B
H'000E to H'000F H'001C to H'001F
H'0010 to H'0011
H'0020 to H'0023
H'0012 to H'0013
H'0024 to H'0027
H'0014 to H'0015
H'0028 to H'002B
H'0016 to H'0017 H'002C to H'002F
H'0018 to H'0019
H'0030 to H'0033
H'001A to H'001B H'0034 to H'0037
H'001C to H'001D H'0038 to H'003B
H'001E to H'001F
⏐
H'0022 to H'0023
H'003C to H'003F
⏐
H'0044 to H'0047
H'0024 to H'0025
H'0048 to H'004B
Rev. 2.00 Oct. 20, 2009 Page 106 of 1340
REJ09B0499-0200