R5F61655N50FPV Datasheet, PDF (766/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 16 8-Bit Timers (TMR)
Table 16.3 Clock Input to TCNT and Count Condition (Unit 1)
TCR
TCCR
Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
TMR_2
0
0
0
⎯ ⎯ Clock input prohibited
0
0
1
0
0
Uses internal clock. Counts at rising edge of Pφ/8.
0
1
Uses internal clock. Counts at rising edge of Pφ/2.
1
0
Uses internal clock. Counts at falling edge of Pφ/8.
1
1
Uses internal clock. Counts at falling edge of Pφ/2.
0
1
0
0
0
Uses internal clock. Counts at rising edge of Pφ/64.
0
1
Uses internal clock. Counts at rising edge of Pφ/32.
1
0
Uses internal clock. Counts at falling edge of Pφ/64.
1
1
Uses internal clock. Counts at falling edge of Pφ/32.
0
1
1
0
0
Uses internal clock. Counts at rising edge of Pφ/8192.
0
1
Uses internal clock. Counts at rising edge of Pφ/1024.
1
0
Uses internal clock. Counts at falling edge of Pφ/8192.
1
1
Uses internal clock. Counts at falling edge of Pφ/1024.
1
0
0
⎯
⎯
Counts at TCNT_3 overflow signal*¹.
TMR_3
0
0
0
⎯
⎯
Clock input prohibited
0
0
1
0
0
Uses internal clock. Counts at rising edge of Pφ/8.
0
1
Uses internal clock. Counts at rising edge of Pφ/2.
1
0
Uses internal clock. Counts at falling edge of Pφ/8.
1
1
Uses internal clock. Counts at falling edge of Pφ/2.
0
1
0
0
0
Uses internal clock. Counts at rising edge of Pφ/64.
0
1
Uses internal clock. Counts at rising edge of Pφ/32.
1
0
Uses internal clock. Counts at falling edge of Pφ/64.
1
1
Uses internal clock. Counts at falling edge of Pφ/32.
0
1
1
0
0
Uses internal clock. Counts at rising edge of Pφ/8192.
0
1
Uses internal clock. Counts at rising edge of Pφ/1024.
1
0
Uses internal clock. Counts at falling edge of Pφ/8192.
1
1
Uses internal clock. Counts at falling edge of Pφ/1024.
1
0
0
⎯
⎯
Counts at TCNT_2 compare match A*¹.
All
1
0
1
⎯
⎯
Uses external clock. Counts at rising edge*².
1
1
0
⎯
⎯
Uses external clock. Counts at falling edge*².
1
1
1
⎯ ⎯ Uses external clock. Counts at both rising and falling
edges*².
Notes: 1. If the clock input of channel 2 is the TCNT_3 overflow signal and that of channel 3 is the
TCNT_2 compare match signal, no incrementing clock is generated. Do not use this
setting.
2. To use the external clock, the DDR and ICR bits in the corresponding pin should be set
to 0 and 1, respectively. For details, see section 13, I/O Ports.
Rev. 2.00 Oct. 20, 2009 Page 734 of 1340
REJ09B0499-0200