R5F61655N50FPV Datasheet, PDF (1082/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 24 Flash Memory
(c) Erasure
FPFR indicates the return value of the erasure result.
Bit
7
6
5
4
3
2
Bit Name
⎯
MD
EE
FK
EB
⎯
1
0
⎯
SF
Initial
Bit
Bit Name Value R/W Description
7
⎯
⎯
⎯
Unused
Returns 0.
6
MD
⎯
R/W Erasure Mode Related Setting Error Detect
Detects the error protection state and returns the result.
When the error protection state is entered, this bit is set
to 1. Whether the error protection state is entered or not
can be confirmed with the FLER bit in FCCS. For
conditions to enter the error protection state, see section
24.9.3, Error Protection.
0: Normal operation (FLER = 0)
1: Error protection state, and programming cannot be
performed (FLER = 1)
5
EE
⎯
R/W Erasure Execution Error Detect
Returns 1 when the user MAT could not be erased or
when the flash memory related register settings are
partially changed. If this bit is set to 1, there is a high
possibility that the user MAT has been erased partially.
In this case, after removing the error factor, erase the
user MAT. If FMATS is set to H'AA and the user boot
MAT is selected, an error occurs when erasure is
performed. In this case, both the user MAT and user
boot MAT have not been erased. Erasing of the user
boot MAT should be performed in boot mode or
programmer mode.
0: Erasure has ended normally
1: Erasure has ended abnormally
Rev. 2.00 Oct. 20, 2009 Page 1050 of 1340
REJ09B0499-0200