R5F61655N50FPV Datasheet, PDF (165/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 7 Interrupt Controller
7.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCR selects the source that generates an interrupt request from IRQ14 and IRQ11 to IRQ0 input.
Upon changing the setting of ISCR, IRQnF (n = 0 to 11, 14) in ISR is often set to 1 accidentally
through an internal operation. In this case, an interrupt exception handling is executed if an IRQn
interrupt request is enabled. In order to prevent such an accidental interrupt from occurring, the
setting of ISCR should be changed while the IRQn interrupt is disabled, and then the IRQnF in
ISR should be cleared to 0.
• ISCRH
Bit
15
14
13
12
11
10
9
8
Bit Name
⎯
⎯
IRQ14SR* IRQ14SF*
⎯
⎯
⎯
⎯
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
Bit Name IRQ11SR
Initial Value
0
R/W
R/W
6
IRQ11SF
0
R/W
5
IRQ10SR
0
R/W
4
IRQ10SF
0
R/W
3
IRQ9SR
0
R/W
2
IRQ9SF
0
R/W
1
IRQ8SR
0
R/W
0
IRQ8SF
0
R/W
• ISCRL
Bit
15
Bit Name IRQ7SR
Initial Value
0
R/W
R/W
Bit
7
Bit Name IRQ3SR
Initial Value
0
R/W
R/W
14
IRQ7SF
0
R/W
6
IRQ3SF
0
R/W
13
IRQ6SR
0
R/W
5
IRQ2SR
0
R/W
12
IRQ6SF
0
R/W
4
IRQ2SF
0
R/W
11
IRQ5SR
0
R/W
3
IRQ1SR
0
R/W
10
IRQ5SF
0
R/W
2
IRQ1SF
0
R/W
9
IRQ4SR
0
R/W
1
IRQ0SR
0
R/W
8
IRQ4SF
0
R/W
0
IRQ0SF
0
R/W
Note: * Supported only by the H8SX/1655M Group.
Rev. 2.00 Oct. 20, 2009 Page 133 of 1340
REJ09B0499-0200