R5F61655N50FPV Datasheet, PDF (331/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 10 DMA Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
11
TSEIE
0
R/W Transfer Size Error Interrupt Enable
Enables/disables a transfer size error interrupt.
When the next transfer is requested while this bit is set
to 1 and the contents of the transfer counter is less than
the size of data to be transferred at a single transfer
request, the DTE bit is cleared to 0. At this time, the
ESIF bit is set to 1 to indicate that a transfer size error
interrupt has been requested.
The sources of a transfer size error are as follows:
• In normal or repeat transfer mode, the total transfer
size set in DTCR is less than the data access size
• In block transfer mode, the total transfer size set in
DTCR is less than the block size
0: Disables a transfer size error interrupt request
1: Enables a transfer size error interrupt request
10
⎯
0
R
Reserved
This bit is always read as 0 and cannot be modified.
9
ESIE
0
R/W Transfer Escape Interrupt Enable
Enables/disables a transfer escape end interrupt
request. When the ESIF bit is set to 1 with this bit set to
1, a transfer escape end interrupt is requested to the
CPU or DTC. The transfer end interrupt request is
cleared by clearing this bit or the ESIF bit to 0.
0: Disables a transfer escape end interrupt
1: Enables a transfer escape end interrupt
8
DTIE
0
R/W Data Transfer End Interrupt Enable
Enables/disables a transfer end interrupt request by the
transfer counter. When the DTIF bit is set to 1 with this
bit set to 1, a transfer end interrupt is requested to the
CPU or DTC. The transfer end interrupt request is
cleared by clearing this bit or the DTIF bit to 0.
0: Disables a transfer end interrupt
1: Enables a transfer end interrupt
Rev. 2.00 Oct. 20, 2009 Page 299 of 1340
REJ09B0499-0200