R5F61655N50FPV Datasheet, PDF (211/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

A block diagram of the bus controller is shown in figure 9.1.
Section 9 Bus Controller (BSC)
CPU address bus
DMAC address bus
DTC address bus
EXDMAC address bus
Address
selector
Area decoder
CS7 to CS0
Internal bus
control signals
CPU bus mastership acknowledge signal
DTC bus mastership acknowledge signal
DMAC bus mastership acknowledge signal
CPU bus mastership request signal
DTC bus mastership request signal
DMAC bus mastership request signal
EXDMAC bus mastership acknowledge signal
EXDMAC bus mastership request signal
Internal bus
control unit
Internal
bus
arbiter
External bus
control unit
External bus
arbiter
External bus
control signals
WAIT
BREQ
BACK
BREQO
Internal data bus
Control register
ABWCR
ASTCR
WTCRA
WTCRB
RDNCR
CSACR
IDLCR
BCR1
BCR2 ENDIANCR
SRAMCR
BROMCR
MPXCR
[Legend]
ABWCR: Bus width control register
ASTCR: Access state control register
WTCRA: Wait control register A
WTCRB: Wait control register B
RDNCR: Read strobe timing control register
CSACR: CS assertion period control register
IDLCD: Idle control register
BCR1:
Bus control register 1
BCR2:
Bus control register 2
ENDIANCR: Endian control register
SRAMCR: SRAM mode control register
BROMCR: Burst ROM interface control register
MPXCR: Address/data multiplexed I/O control register
Figure 9.1 Block Diagram of Bus Controller
Rev. 2.00 Oct. 20, 2009 Page 179 of 1340
REJ09B0499-0200