R5F61655N50FPV Datasheet, PDF (911/1376 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 19 USB Function Module (USB)
19.3.8 Interrupt Enable Register 1 (IER1)
IER1 enables the interrupt requests of interrupt flag register 1 (IFR1). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 1
(ISR1).
Bit
7
6
5
4
3
2
1
0
Bit Name
⎯
⎯
⎯
⎯
⎯
EP3 TR
EP3 TS
VBUSF
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R/W
R/W
R/W
Initial
Bit Bit Name Value R/W Description
7
⎯
0
R
Reserved
6
⎯
5
⎯
0
R
These bits are always read as 0. The write value
0
R
should always be 0.
4
⎯
0
R
3
⎯
0
R
2
EP3 TR
0
R/W EP3 Transfer Request
1
EP3 TS
0
R/W EP3 Transmission Complete
0
VBUSF
0
R/W USB Bus Connect
19.3.9 Interrupt Enable Register 2 (IER2)
IER2 enables the interrupt requests of interrupt flag register 2 (IFR2). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 2
(ISR2).
Bit
7
6
Bit Name SSRSME
⎯
Initial Value
0
0
R/W
R/W
R
5
4
3
⎯
SURSE
CFDN
0
0
0
R
R/W
R/W
2
1
0
⎯
SETCE
SETIE
0
0
0
R
R/W
R/W
Rev. 2.00 Oct. 20, 2009 Page 879 of 1340
REJ09B0499-0200