HD151TS207SS Datasheet, PDF (9/38 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS207SS
I²C Controlled Register Bit Map (cont.)
Table4 CPU Clock Power Management Truth Table
Signal
Pin
PWRDWN#
PWRDWN#
Tristate Bit
Byte2[5:3]
CPU[2:0]
1
X
CPU[2:0]
0
0
CPU[2:0]
0
1
Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA,
Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 Ω)
Non-Stop
Outputs
Byte1[5:3] = 1
Running
Driven @ Iref x2
Tristate
Note
See Note1
Table5 SRC Clock Power Management Truth Table
Signal Pin
Pin
PCI_STOP# PWRDWN# Non-Stop Stoppable Note
PWRDWN# PCI_STOP# Tristate Bit Tristate Bit Outputs Outputs
Byte2[6] Byte2[7] Byte1[7] = 1 Byte1[7] = 0
SRC 1
1
X
X
Running
Running
SRC 1
0
0
X
Running
Driven @ See Note1
Iref x6
SRC 1
0
1
X
Running
Tristate
SRC 0
X
X
0
Driven @ Driven @ See Note1
Iref x2
Iref x2
SRC 0
X
X
1
Tristate
Tristate
Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA
Iref x6 = 13.9 mA (Voh @Z: 0.7 V @50 Ω)
Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 Ω)
Byte3 Control Register
Bit Description
7
PCI_Stop control
6
PCI_6 Output enable
5
PCI_5 Output enable
4
PCI_4 Output enable
3
PCI_3 Output enable
2
PCI_2 Output enable
1
PCI_1 Output enable
0
PCI_0 Output enable
Contents
0 = Enabled, all stoppable PCI
and SRC clocks are stopped.
1 = Disabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
Type Default Note
RW 1
RW 1
RW 1
RW 1
RW 1
RW 1
RW 1
RW 1
Rev.1.00, Apr.25.2003, page 9 of 38