HD151TS207SS Datasheet, PDF (23/38 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS207SS
I²C Controlled Register Bit Map (cont.)
Byte28 Control Register
Bit Description
Contents
Type
7
Reserved
0 = Normal, 1 = Late
R/W
6
PCI_6 Skew Select Bit
0 = Normal, 1 = Late
R/W
5
PCI_5 Skew Select Bit
0 = Normal, 1 = Late
R/W
4
PCI_4 Skew Select Bit
0 = Normal, 1 = Late
R/W
3
PCI_3 Skew Select Bit
0 = Normal, 1 = Late
R/W
2
PCI_2 Skew Select Bit
0 = Normal, 1 = Late
R/W
1
PCI_1 Skew Select Bit
0 = Normal, 1 = Late
R/W
0
PCI_0 Skew Select Bit
0 = Normal, 1 = Late
R/W
Note: 1. Normal = Skew1(B26[3:0]), Late = Skew1(B26[3:0]) +Skew2 (B26[7:4]).
Default
0
0
0
0
0
0
0
0
Note
See
Note
1
Byte29 Control Register
Bit Description
Contents
7
VCH Slew Rate Control Bit1 00 = Normal, 10 = “++”
6
VCH Slew Rate Control Bit0 ^{01 = “+“ , 11 = “–”}
5
PCI Slew Rate Control Bit1 00 = Normal, 10 = “++”
4
PCI Slew Rate Control Bit0 ^{01 = “+“ , 11 = “–”}
3
PCIF Slew Rate Control Bit1 00 = Normal, 10 = “++”
2
PCIF Slew Rate Control Bit0 ^{01 = “+“ , 11 = “–”}
1
3V66 Slew Rate Control Bit1 00 = Normal, 10 = “++”
0
3V66 Slew Rate Control Bit0 ^{01 = “+“ , 11 = “–”}
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
0
1
0
1
0
1
0
Note
Rev.1.00, Apr.25.2003, page 23 of 38