HD151TS207SS Datasheet, PDF (21/38 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS207SS
I²C Controlled Register Bit Map (cont.)
Byte24 Control Register
Bit Description
7
Reserved
6
PCI_STOP# Stop PCI_6
Control Bit
5
PCI_STOP# Stop PCI_5
Control Bit
4
PCI_STOP# Stop PCI_4
Control Bit
3
PCI_STOP# Stop PCI_3
Control Bit
2
PCI_STOP# Stop PCI_2
Control Bit
1
PCI_STOP# Stop PCI_1
Control Bit
0
PCI_STOP# Stop PCI_0
Control Bit
Contents
0 = Stoppable, 1 = Free running
0 = Stoppable, 1 = Free running
0 = Stoppable, 1 = Free running
0 = Stoppable, 1 = Free running
0 = Stoppable, 1 = Free running
0 = Stoppable, 1 = Free running
0 = Stoppable, 1 = Free running
Type
R/W
R/W
Default
0
0
Note
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Byte25 Control Register
Bit Description
Contents
7
CPU Clock Skew1 Control
Delay
Ahead
Bit3
1000 = +0.00ns, 0111 = –0.20ns
6
CPU Clock Skew1 Control
1001 = +0.20ns, 0110 = –0.40ns
Bit2
1010 = +0.40ns, 0101 = –0.60ns
1011 = +0.60ns, 0100 = –0.80ns
5
CPU Clock Skew1 Control _{1100 = +0.80ns, 0011 = –1.00ns}
Bit1
1101 = +1.00ns, 0010 = –1.20ns
4
CPU Clock Skew1 Control ^{1110 = +1.20ns, 0001 = –1.40ns}
Bit0
1111 = +1.40ns, 0000 = –1.60ns
3
CPU Clock Skew2 Control
Delay
Ahead
Bit3
1000 = +0.00ns, 0111 = –0.15ns
2
CPU Clock Skew2 Control
1001 = +0.15ns, 0110 = –0.30ns
Bit2
1010 = +0.30ns, 0101 = –0.45ns
1011 = +0.45ns, 0100 = –0.60ns
1
CPU Clock Skew2 Control _{1100 = +0.60ns, 0011 = –0.75ns}
Bit1
1101 = +0.75ns, 0010 = –0.90ns
0
CPU Clock Skew2 Control ^{1110 = +0.90ns, 0001 = –1.05ns}
Bit0
1111 = +1.05ns, 0000 = –1.20ns
Note: 1. Total CPU Clock Skew is Skew1+Skew2.
Type
R/W
R/W
Default
1
0
Note
See
Note
1
R/W 0
R/W 0
R/W 1
R/W 0
See
Note
1
R/W 0
R/W 0
Rev.1.00, Apr.25.2003, page 21 of 38