HD151TS207SS Datasheet, PDF (22/38 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS207SS
I²C Controlled Register Bit Map (cont.)
Byte26 Control Register
Bit Description
Contents
Type
7
PCIF / PCI Clock Skew2
Control Bit3
6
PCIF / PCI Clock Skew2
Control Bit2
5
PCIF / PCI Clock Skew2
Control Bit1
4
PCIF / PCI Clock Skew2
Control Bit0
Skew2 is “Late” Skew that is Delay
R/W
Time from “Normal” Skew1.
0000 = +0.0ns, 1000 = +3.2ns
R/W
0001 = +0.4ns, 1001 = +3.6ns
0010 = +0.8ns, 1010 = +4.0ns
0011 = +1.2ns, 1011 = +4.4ns
R/W
0100 = +1.6ns, 1100 = +4.8ns
0101 = +2.0ns, 1101 = +5.2ns
R/W
0110 = +2.4ns, 1110 = +5.6ns
0111 = +2.8ns, 1111 = +6.0ns
3
PCIF / PCI Clock Skew1
Skew1 is “Normal” Skew.
R/W
Control Bit3
Delay
Ahead
2
PCIF / PCI Clock Skew1
1000 = +0.0ns, 0111 = –0.4ns
R/W
Control Bit2
1001 = +0.4ns, 0110 = –0.8ns
1010 = +0.8ns, 0101 = –1.2ns
1
PCIF / PCI Clock Skew1
1011 = +1.2ns, 0100 = –1.6ns
R/W
Control Bit1
1100 = +1.6ns, 0011 = –2.0ns
0
PCIF / PCI Clock Skew1
1101 = +2.0ns, 0010 = –2.4ns
R/W
Control Bit0
1110 = +2.4ns, 0001 = –2.8ns
1111 = +2.8ns, 0000 = –3.2ns
Note: 1. PCIF / PCI Clock Skew is Skew1 (= Normal) or Skew1+Skew2 (= Late).
Default
0
0
Note
See
Note
1
0
0
1
See
Note
0
1
0
0
Byte27 Control Register
Bit Description
Contents
Type
7
Reserved
R/W
6
PCIF_2 Skew Select Bit
0 = Normal, 1 = Late
R/W
5
PCIF_1 Skew Select Bit
0 = Normal, 1 = Late
R/W
4
PCIF_0 Skew Select Bit
0 = Normal, 1 = Late
R/W
3
3V66 Clock Skew Control
Bit3
Delay
Ahead
1000 = +0.0ns, 0111 = –0.4ns
R/W
2
3V66 Clock Skew Control
Bit2
1001 = +0.4ns, 0110 = –0.8ns
1010 = +0.8ns, 0101 = –1.2ns
R/W
1011 = +1.2ns, 0100 = –1.6ns
1
3V66 Clock Skew Control
Bit1
1100 = +1.6ns, 0011 = –2.0ns
1101 = +2.0ns, 0010 = –2.4ns
R/W
0
3V66 Clock Skew Control
Bit0
1110 = +2.4ns, 0001 = –2.8ns
1111 = +2.8ns, 0000 = –3.2ns
R/W
Note: 1. Normal = Skew1(B26[3:0]), Late = Skew1(B26[3:0]) +Skew2 (B26[7:4]).
Default
0
0
0
0
Note
See
Note
1
1
0
0
0
Rev.1.00, Apr.25.2003, page 22 of 38