HD151TS207SS Datasheet, PDF (14/38 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS207SS
I²C Controlled Register Bit Map (cont.)
Byte10 Control Register
Bit Description
7
SSC Spread Select Bit[2:0]
6
5
4
Backup of latch Input FS_4 at
Power ON
3
Backup of latch Input FS_3 at
Power ON
2
Backup of latch Input FS_2 at
Power ON
1
Backup of latch Input FS_A at
Power ON
0
Backup of latch Input FS_B at
Power ON
Contents
Bit[2:0] =
000 = –0.500%, 100 = ±0.250%
001 = –0.750%, 101 = ±0.375%
010 = –1.000%, 110 = ±0.500%
011 = –1.500%, 111 = ±0.750%
When SAFE_F# is Enable
(B15[5]=1)
PWRDWN#/SAFE_F# pin to
“Low”, and if B23[1]=0, frequency
selection is changed to these
setting and
PWRDWN#/SAFE_F# pin to
“High”, frequency selection is
changed back to the last mode.
Type
RW
RW
RW
R
R
R
R
R
Default
0
0
0
Note
X
X
X
X
X
Byte11 Control Register
Bit Description
Contents
Type Default Note
7
PCI_STOP# Enable Control Bit 0 = Enable , 1 = Disable
RW 0
6
CPU_STOP# Enable Control Bit 0 = Enable , 1 = Disable
RW 0
5
PWRDWN# Enable Control Bit 0 = Enable , 1 = Disable
RW 0
4
Backup of B9[5] written by I²C
When SAFE_F# is Enable
R
X
3
Backup of B9[4] written by I²C
(B15[5]=1)
R
X
PWRDWN#/SAFE_F# pin to
2
Backup of B9[3] written by I²C
“Low”, and if B23[1]=1,
R
X
1
Backup of B9[2] written by I²C
frequency selection is changed to _R
X
0
Backup of B9[1] written by I²C
these setting and
PWRDWN#/SAFE_F# pin to
R
X
“High”, frequency selection is
changed back to the last mode.
Rev.1.00, Apr.25.2003, page 14 of 38