HD151TS207SS Datasheet, PDF (8/38 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS207SS
I²C Controlled Register Bit Map (cont.)
Table3 FS_A and FS_B pin Input level
Logic Level
0 (Low)
1 (High)
Min Voltage

0.70V
Max Voltage
0.35V

Byte1 Control Register
Bit Description
Contents
7
Allow control of SCR with assertion 0 = Free running
of PCI_STOP#
1 = Stopped with
PCI_STOP#
6
SRC Output enable
0 = Disabled (tristate)
1 = Enabled
5
Reserved
4
Reserved
3
Reserved
2
CPU2 Output enable
0 = Disabled (tristate)
1 = Enabled
1
CPU1 Output enable
0 = Disabled (tristate)
1 = Enabled
0
CPU0 Output enable
0 = Disabled (tristate)
1 = Enabled
Type
RW
Default
0
Note
See
Table5
RW 1
RW 1
RW 1
RW 1
RW 1
RW 1
RW 1
Byte2 Control Register
Bit Description
7
SRC_Pwrdwn drive mode
6
SRC_Stop drive mode
5
CPU2_Pwrdwn drive mode
4
CPU1_Pwrdwn drive mode
3
CPU0_Pwrdwn drive mode
2
Reserved
1
Reserved
0
Reserved
Contents
0 = Driven in power down,
1 = Tristate
0 = Driven when stopped,
1 = Tristate
0 = Driven in power down,
1 = Tristate
0 = Driven in power down,
1 = Tristate
0 = Driven in power down,
1 = Tristate
Type
RW
RW
Default
0
0
Note
See
Table5
RW 0
RW 0
See
Table4
RW 0
RW 0
RW 0
RW 0
Rev.1.00, Apr.25.2003, page 8 of 38