HD151TS207SS Datasheet, PDF (12/38 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS207SS
I²C Controlled Register Bit Map (cont.)
Byte9 Control Register
Bit Description
Contents
Type Default Note
7
SSC2 Enable Bit
B6[2] = 0 or B9[7] = 1 : SSC2 =OFF RW 0
B6[2] = 1 & B9[7] = 0 : SSC2 = ON
6
SSC1 Enable Bit
B6[2] = 0 or B9[6] = 1 : SSC1 = OFF RW 0
B6[2] = 1 & B9[6] = 0 : SSC1 = ON
5
Clock Frequency Control Latched input PCIF_1 at Power ON RW X
Bit4
4
Clock Frequency Control Latched input DOT48 at Power ON RW X
Bit3
See
Table
6
3
Clock Frequency Control Latched input PCIF_0 at Power ON RW X
Bit2
2
Clock Frequency Control Latched input FS_A at Power ON
Bit1
RW X
1
Clock Frequency Control Latched input FS_B at Power ON
Bit0
RW X
0
Frequency Select Mode Bit 0 = Freq. is selected by latched input RW 0
FS_A and FS_B
1 = Freq. is selected by I²C B9[5:1]
Rev.1.00, Apr.25.2003, page 12 of 38