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HD151TS207SS Datasheet, PDF (29/38 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)
HD151TS207SS
DC Electrical Characteristics CPU/CPU# Clock
Ta = 0°C to 70°C, VDD = 3.3 V, Iref = 475 Ω
Item
Symbol Min
Typ *1 Max
Unit Test Conditions
Output voltage
Output Current
VO


1.20
V
Rp = 49.9 Ω, VDD = 3.3 V
IO

I(nom) *2 
mA VDD = 3.3 V
Output resistance
3000 

Ω
VO = 1.2 V
Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditionaI (nom) is output current(Ioh) shown in below.
2. Ioh = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA,
Ioh x6 = 13.89 mA (Voh @Z: 0.695 V @50 Ω),
Ioh x2 = 4.63 mA (Voh @Z: 0.232 V @50 Ω)
AC Electrical Characteristics CPU/CPU# Clock (CPU at 0.7V Timing)
Ta = 0°C to 70°C, VDD = 3.3 V, CL = 2 pF, Rs = 33.2 Ω, Rp = 49.9 Ω
Item
Cycle to cycle jitter
CPU Group Skew
(CPU clock out to
CPU clock out)
Rise time
Fall time
Symbol Min
tCCS

tskS

Typ
Max
|125| 
|100| 
Unit Test Conditions Notes
ps
Note1
ps
tr
175

700
ps VO = 0.175 V
200MHz
to 0.525 V
tf
175

700
ps VO = 0.175 V
200MHz
to 0.525 V
Clock Duty Cycle
45
50
55
%
CPU clock period(100)

9.99

ns
CPU clock period(133)

7.49

ns
CPU clock period(166)

5.99

ns
CPU clock period(200)

4.99

ns
Cross point(0.7V) voltage Vcross 0.25

0.55
V
Note: 1. Difference of cycle time between two adjoining cycles.
200MHz
200MHz
Rev.1.00, Apr.25.2003, page 29 of 38