HD151TS207SS Datasheet, PDF (20/38 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS207SS
I²C Controlled Register Bit Map (cont.)
Byte22 Control Register
Bit Description
7
CPU Frequency Read Bit7
6
CPU Frequency Read Bit6
5
CPU Frequency Read Bit5
4
CPU Frequency Read Bit4
3
CPU Frequency Read Bit3
2
CPU Frequency Read Bit2
1
CPU Frequency Read Bit1
0
CPU Frequency Read Bit0
Contents
Calculation result of CPU frequency.
1 MHz digit
0000 = 0, 0001 = 1 …. 1001 = 9
Calculation result of CPU frequency.
0.1 MHz digit
0000 = 0, 0001 = 1 …. 1001 = 9
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Note
Byte23 Control Register
Bit Description
Contents
Type Default Note
7
Watchdog Enable Control Bit 0 = Disable , Pin22 = 3V66_0 output R/W 0
1 = Enable , Pin22 = RESET# output
6
RESET# Reverse Control Bit 0 = Normal , 1 = Reverse
R/W 0
5
Watchdog Timer Count Bit3 These 4 bits corresponds to how
R/W 1
4
Watchdog Timer Count Bit2 ^{many watchdog timer will wait from}
R/W 0
becoming “Alarm mode” (B23[0] = 1)
3
Watchdog Timer Count Bit1 _{to outputting RESET# pin to “Low”.}
R/W 0
2
Watchdog Timer Count Bit0 ^{Default is 586ms x8 = 4.7s at Power} R/W 0
ON
1
Backup Frequency Select Bit 0 = B10[4:0] , 1 = B11[4:0]
R/W 0
When SAFE_F# is “Low” , frequency
mode is changed to the predefined
frequency mode decided by B10[4:0]
or B11[4:0].
0
Watchdog Status Bit
0 = Normal mode, 1 = Alarm mode
R/W 0
Rev.1.00, Apr.25.2003, page 20 of 38