HD151TS207SS Datasheet, PDF (15/38 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS207SS
I²C Controlled Register Bit Map (cont.)
Byte12 Control Register
Bit Description
Contents
Type Default Note
7
Reserved
R/W 0
6
Reserved
R/W 0
5
Reserved
R/W 0
4
Reserved
R/W 0
3
Reserved
R/W 0
2
PLL1 Output (VCO1) Frequency 0 = Normal mode
R/W 0
Control Bit
PLL1 M1[6:0] and N1[9:0] are
(M1/N1 Divider Control Bit)
changed on Table 5 selection
PLL1 : for SRC/3V66/PCI_PLL decided by FS4/3/2/A/B or
B9[5:1]
1 = Over or Down clocking mode
PLL1 M1[6:0] and N1[9:0] are
changed by B12[1:0], B13[7:0]
and B14[6:0].
B12[1:0], B13[7:0] and B14[6:0]
are able to be changed at B12[2]
= 1.
See.
Note
1
1
PLL1 N1 Divider Control Bit9
N1[9]
R/W 0
0
PLL1 N1 Divider Control Bit8
N1[8]
R/W 0
Note: 1. B12[1:0], B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.
Byte13 Control Register
Bit Description
Contents
Type Default Note
7
PLL1 N1 Divider Control Bit7
6
PLL1 N1 Divider Control Bit6
5
PLL1 N1 Divider Control Bit5
N1[7]
N1[6]
N1[5]
R/W 0
R/W 1
R/W 0
See
Note
1
4
PLL1 N1 Divider Control Bit4
N1[4]
R/W 0
3
PLL1 N1 Divider Control Bit3
N1[3]
R/W 1
2
PLL1 N1 Divider Control Bit2
N1[2]
R/W 0
1
PLL1 N1 Divider Control Bit1
N1[1]
R/W 1
0
PLL1 N1 Divider Control Bit0
N1[0]
R/W 1
Note: 1. B12[1:0], B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.
Rev.1.00, Apr.25.2003, page 15 of 38