HD151TS207SS Datasheet, PDF (24/38 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS207SS
Clock Stop Timing Diagram
PCI_STOP# Assertion/De-assersion
PCI_STOP#
PCI_F
PCI
SRC (Stoppable)
SRC (Stoppable)
SRC# (Stoppable)
Low
6× Iref (Controled by Byte2[6])
Tristate (Controled by Byte2[6])
Tristate
PCI_STOP# Assertion/De-assertion Waveforms
PWRDWN# Assertion/De-assersion
PWRDWN#
CPU (Stoppable)
CPU (Stoppable)
CPU# (Stoppable)
2× Iref (Controled by Byte2[5:3])
Float (Controled by Byte2[5:3])
Float
PWRDWN# Assertion/De-assertion Waveforms
< 1.8 ms
6× Iref
6× Iref
PWRDWN# Functionality
PWRDWN#
1
0
CPU
Normal
Iref:2
or Float
CPU# SRC
Normal Normal
Iref:2
Float _{or Float}
SRC#
Normal
Float
3V66 PCIF/PCI
66MHz 33MHz
Low
Low
USB/DOT
48MHz
Low
REF
14.318MHz
Low
Rev.1.00, Apr.25.2003, page 24 of 38