HD151TS207SS Datasheet, PDF (7/38 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS207SS
I²C Controlled Register Bit Map
Byte0 Control Register
Bit Description
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 PCI_Stop Reflects the current value
of the external PCI_STOP# pin
2 Reserved
1 FS_B Reflects the value of the
FS_B pin sampled on power up
0 FS_A Reflects the value of the
FS_A pin sampled on power up
Contents
0 = PCI_STOP# pin is Low
1 = PCI_STOP# pin is High
0 = FS_B Low at power up
1 = FS_B High at power up
0 = FS_A Low at power up
1 = FS_A High at power up
Type
R
R
R
R
R
Default
0
0
0
0
X
Note
R
X
R
X
R
X
See
Table
1
Table1 Clock Frequency Function Table
Byte6
Bit5
FS_A
FS_B
CPU
[MHz]
SRC
[MHz]
3V66
[MHz]
0
0
0
100
100/200 66
0
0
1
200
100/200 66
0
1
0
133
100/200 66
0
1
1
166
100/200 66
1
0
0
200
100/200 66
1
0
1
400
100/200 66
1
1
0
266
100/200 66
1
1
1
333
100/200 66
PCIF
PCI
[MHz]
33
33
33
33
33
33
33
33
REF0
REF1
[MHz]
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
USB
DOT
[MHz]
48
48
48
48
48
48
48
48
Note
Table2 Test Clock select table
TEST_CLK# CPU
[MHz]
SRC
[MHz]
3V66
[MHz]
PCIF
PCI
[MHz]
REF0
REF1
[MHz]
1
REF/2 REF/2
REF/4
REF/8
REF
0
Hi–Z
Hi–Z
Hi–Z
Hi–Z
Hi–Z
Note: 1. REF is a clock over driven on the XIN during test mode.
USB
DOT
[MHz]
REF/2
Hi–Z
Note
See Note1,
Table3
Rev.1.00, Apr.25.2003, page 7 of 38