UPD70F3793GC-UEU-AX Datasheet, PDF (887/1113 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-L Microcontrollers

V850ES/JG3-L
CHAPTER 25 CLOCK MONITOR
(3) Operation in STOP mode or after STOP mode is released
If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and
while the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor
operation is automatically started.
Figure 25-4. Operation in STOP Mode or After STOP Mode Is Released
CPU Normal
operation operation
Main clock
STOP
Oscillation stabilization time
Internal oscillator
clock
Oscillation stops ^{Oscillation stabilization time}
(set by OSTS register)
CLME
Clock monitor
status
During
monitor
Monitor stops
Normal operation
During monitor
(4) Operation when main clock is stopped (arbitrary)
During subclock operation (PCC.CLS bit = 1) or when the main clock is stopped by setting the PCC.MCK bit to
1, the monitor operation is stopped until the main clock operation is started (PCC.CLS bit = 0). The monitor
operation is automatically started when the main clock operation is started.
Figure 25-5. Operation When Main Clock Is Stopped (Arbitrary)
CPU
operation
Main clock
Internal oscillator
clock
Subclock operation
PCC.MCK bit = 1 Oscillation stabilization
time count by software
Oscillation stops
CLME
Clock monitor
status
During Monitor stops
monitor
Monitor stops
Main clock operation
During monitor
(5) Operation while CPU is operating on internal oscillator clock (CCLS.CCLSF bit = 1)
The monitor operation is not stopped when the CCLSF bit is 1, even if the CLME bit is set to 1.
R01UH0165EJ0700 Rev.7.00
Sep 22, 2011
Page 887 of 1113