UPD70F3793GC-UEU-AX Datasheet, PDF (746/1113 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-L Microcontrollers

V850ES/JG3-L
CHAPTER 19 I²C BUS
19.16.1 Master operation in single master system
Figure 19-18. Master Operation in Single Master System
START
Initialize I²C bus^Note
Set ports
IICXn ← 0XH
IICCLn ← XXH
OCKSm ← XXH
Refer to Table 4-15 Settings When Pins Are Used for Alternate Functions
to set the I²C mode before this function is used.
Transfer clock selection
SVAn ← XXH
Local address setting
IICFn ← 0XH
Start condition setting
Set STCENn, IICRSVn = 0
IICCn ← XXH
ACKEn = WTIMn = SPIEn = 1
IICEn = 1
STCENn = 1?
No
SPTn = 1
Yes
Communication start preparation
(stop condition generation)
INTIICn
interrupt occurred?
Yes
No
Waiting for stop condition detection
STTn = 1
Write IICn
Communication start preparation
(start condition generation)
Communication start
(address, transfer direction specification)
INTIICn
interrupt occurred?
Yes
No
Waiting for ACK detection
No
ACKDn = 1?
Yes
TRCn = 1?
No
Yes
Write IICn
Transmission start
INTIICn
interrupt occurred?
Yes
No
Waiting for data transmission
ACKDn = 1?
No
Yes
No
Transfer completed?
Yes
Restarted?
Yes
No
SPTn = 1
END
ACKEn = 1
WTIMn = 0
WRELn = 1
Reception start
INTIICn
interrupt occurred?
Yes
Read IICn
No
Waiting for
data reception
Transfer completed?
No
Yes
ACKEn = 0
WTIMn = WRELn = 1
INTIICn
interrupt occurred?
Yes
No
Waiting for ACK detection
Note Release the I²C0n bus (SCL0n, SDA0n pins = high level) in compliance with the specifications of the
product involved in the communication.
For example, when the EEPROM^TM outputs a low level to the SDA0n pin, set the SCL0n pin as an
output pin and output clock pulses from that output pin until the SDA0n pin is constantly high level.
Remarks 1. For the transmission and reception formats, conform to the specifications of the product involved
in the communication.
2. n = 0 to 2, m = 0, 1
R01UH0165EJ0700 Rev.7.00
Sep 22, 2011
Page 746 of 1113