UPD70F3793GC-UEU-AX Datasheet, PDF (212/1113 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-L Microcontrollers

V850ES/JG3-L
CHAPTER 5 BUS CONTROL FUNCTION
Figure 5-13. Separate Bus Write Timing (Bus Size: 16 Bits, 16-bit Access)
(μ PD70F3737, 70F3738, 70F3792, 70F3793 only)
CLKOUT
WAIT
A21 to A0
WR1, WR0
AD15 to AD0
T1
T2
A1
11
00
11
D1
T1
TW
TW
T2
T1
T2
A2
A3
11
00
11
00
11
D2
D3
Programmable External
wait
wait
Remarks 1. The validity of data if 8-bit access is executed when 16-bit access has been specified is shown
below.
8-bit access
Odd address
Even address
AD15 to AD8
Valid data
Invalid data
AD7 to AD0
Invalid data
Valid data
WR1, WR0
01
10
2. The broken lines indicate high impedance.
Figure 5-14. Separate Bus Write Timing (Bus Size: 8 Bits) (μ PD70F3737, 70F3738, 70F3792, 70F3793 only)
CLKOUT
WAIT
A21 to A0
WR1, WR0
AD7 to AD0
T1
T2
A1
11
10
11
D1
T1
TW
TW
T2
T1
T2
A2
A3
11
10
11
10
11
D2
D3
Programmable External
wait
wait
Remark The broken lines indicate high impedance.
R01UH0165EJ0700 Rev.7.00
Sep 22, 2011
Page 212 of 1113