UPD70F3793GC-UEU-AX Datasheet, PDF (703/1113 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-L Microcontrollers

V850ES/JG3-L
CHAPTER 19 I²C BUS
(7) IIC division clock select registers 0, 1 (OCKS0, OCKS1)
The OCKSm register controls the I²C0n division clock (n = 0 to 2, m = 0, 1).
These registers control the I²C00 division clock via the OCKS0 register and the I²C01 and I²C02 division
clocks via the OCKS1 register.
These registers can be read or written in 8-bit units.
Reset sets these registers to 00H.
After reset: 00H R/W Address: OCKS0 FFFFF340H, OCKS1 FFFFF344H
OCKSm
0
0
0 OCKSENm OCKSTHm 0 OCKSm1 OCKSm0
(m = 0, 1)
OCKSENm
Operation setting of I²C division clock
0 Disable I²C division clock operation
1 Enable I²C division clock operation
OCKSTHm OCKSm1 OCKSm0
Selection of I²C division clock
0
0
0
fXX/2
0
0
1
fXX/3
0
1
0
fXX/4
0
1
1
fXX/5
1
0
0
fXX
Other than above
Setting prohibited
(8) IIC shift registers 0 to 2 (IIC0 to IIC2)
The IICn register is used for serial transmission/reception (shift operations) synchronized with the serial
clock. These registers can be read or written in 8-bit units, but data should not be written to the IICn register
during a data transfer.
Access (read/write) the IICn register only during the wait period. Accessing this register in communication
states other than the wait period is prohibited. However, for the master device, the IICn register can be
written once only after the transmission trigger bit (IICCn.STTn bit) has been set to 1.
A wait state is released by writing the IICn register during the wait period, and data transfer is started (n = 0
to 2).
Reset sets these registers to 00H.
After reset: 00H
7
IICn
(n = 0 to 2)
R/W
6
Address: IIC0 FFFFFD80H, IIC1 FFFFFD90H, IIC2 FFFFFDA0H
5
4
3
2
1
0
R01UH0165EJ0700 Rev.7.00
Sep 22, 2011
Page 703 of 1113