UPD70F3793GC-UEU-AX Datasheet, PDF (236/1113 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-L Microcontrollers

V850ES/JG3-L
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
(1) 16-bit counter
This is a 16-bit counter that counts internal clocks and external events.
This counter can be read by using the TPnCNT register.
When the TPnCTL0.TPnCE bit is 0 and the counter is stopped, the counter value is FFFFH. If the TPnCNT
register is read at this time, 0000H is read.
Reset sets the TPnCE bit to 0, stopping the counter, and setting its value to FFFFH.
(2) TMPn counter read buffer register (TPnCNT)
This is a read buffer register from which the value of the 16-bit counter can be read.
(3) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
These registers can be used as either capture registers or compare registers, in accordance with the
specified mode.
(4) CCR0 buffer register
This is a 16-bit compare register that compares the value of the 16-bit counter.
When the TPnCCR0 register is used as a compare register, the value written to the TPnCCR0 register is
transferred to the CCR0 buffer register. If the value of the 16-bit counter matches the value of the CCR0
buffer register, a compare match interrupt request signal (INTTPnCC0) is generated.
The CCR0 buffer register cannot be read or written directly.
The CCR0 buffer register is cleared to 0000H after reset because the TPnCCR0 register is cleared to 0000H.
(5) CCR1 buffer register
This is a 16-bit compare register that compares the value of the 16-bit counter.
When the TPnCCR1 register is used as a compare register, the value written to the TPnCCR1 register is
transferred to the CCR1 buffer register. If the count value of the 16-bit counter matches the value of the
CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated.
The CCR1 buffer register cannot be read or written directly.
The CCR1 buffer register is cleared to 0000H after reset because the TPnCCR1 register is cleared to 0000H.
(6) TMPn control registers 0 and 1 (TPnCTL0 and TPnCTL1)
These are 8-bit registers that control the operations of TMPn.
(7) TMPn I/O control registers 0 to 2 (TPnIOC0 to TPnIOC2)
These are 8-bit registers that control the input and output of TMPn.
(8) TMPn option register 0 (TPnOPT0)
This is an 8-bit register that controls the specification of settings such as capture and compare.
(9) Edge detector
This circuit detects the valid edges input to the TIPn0 and TIPn1 pins. No edge, rising edge, falling edge, or
both the rising and falling edges can be selected as the valid edge by using the TPnIOC1 and TPnIOC2
registers.
R01UH0165EJ0700 Rev.7.00
Sep 22, 2011
Page 236 of 1113