UPD70F3793GC-UEU-AX Datasheet, PDF (853/1113 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-L Microcontrollers

V850ES/JG3-L
CHAPTER 23 STANDBY FUNCTION
Table 23-11. Operating Status in Subclock Operation Mode
Setting of Subclock Operation Mode
Item
Operating Status
When Main Clock Is Oscillating
When Main Clock Is Stopped
LVI
Operable
Subclock oscillator
Oscillates
Internal oscillator
PLL
Oscillation enabled
Operable
Stops operation^Note1
CPU
Operable
DMA
Operable
Interrupt controller
Operable
Timer P (TMP0 to TMP5)
Operable
Stops operation
Timer Q (TMQ0)
Operable
Stops operation
Timer M (TMM0)
Watch timer(/RTC) ^Note2
Operable
Operable
Operable when fR/8 or fXT is selected as
the count clock
Operable when fXT is selected as the
count clock
Watchdog timer 2
Operable
Operable when fR or fXT is selected as the
count clock
Serial interface CSIB0 to CSIB4
I²C00 to I²C02
Operable
Operable
Operable when the SCKBn input clock is
selected as the count clock (n = 0 to 4)
Stops operation
UARTA0 to UARTA5 Operable
UARTC0 ^Note2
Operable
Stops operation (but UARTA0 is operable
when the ASCKA0 input clock is selected)
Stops operation
A/D converter
Operable
Stops operation
D/A converter
Operable
Real-time output function (RTO)
Operable
Stops operation (output held)
Key interrupt function (KR)
Operable
CRC operation circuit
Operable
External bus interface
See 2.2 Pin States.
Port function
Settable
CPU register set
Settable
Internal RAM
Notes 1. Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
2. μ PD70F3792, 70F3793, 70F3841, 70F3842 only
Caution When the CPU is operating on the subclock and main clock oscillation is stopped, a register for
which a wait has been specified must not be accessed. If a wait is generated, it can only be
canceled by a reset (see 3.4.8 (2)).
R01UH0165EJ0700 Rev.7.00
Sep 22, 2011
Page 853 of 1113