UPD70F3793GC-UEU-AX Datasheet, PDF (359/1113 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-L Microcontrollers

V850ES/JG3-L
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Figure 8-8. Register Settings in Interval Timer Mode (3/3)
(g) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3)
Usually, the TQ0CCR1 to TQ0CCR3 registers are not used in the interval timer mode. However,
because the set values of the TQ0CCR1 to TQ0CCR3 registers are transferred to the CCR1 to CCR3
buffer registers and a compare match interrupt request signal (INTTQ0CC1 to INTTQ0CC3) is
generated when the value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer
registers, interrupts from these registers must be masked by setting the interrupt mask flags
(TQ0CCMK1 to TQ0CCMK3).
Remark TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not
used in the interval timer mode.
R01UH0165EJ0700 Rev.7.00
Sep 22, 2011
Page 359 of 1113