UPD70F3793GC-UEU-AX Datasheet, PDF (651/1113 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-L Microcontrollers

V850ES/JG3-L
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
Figure 18-12. Single Transfer Mode Operation Timing (Slave Mode, Transmission Mode)
CBnTSF bit
INTCBnR signal
SCKBn pin
SOBn pin
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(1) (4) (5)
(6) (7)
(8)
(2)
(3)
(1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) =
external clock (SCKBn), and slave mode.
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C1H to the CBnCTL0 register, and select the transmission mode and MSB first at the same time
as enabling the operation of the communication clock (fCCLK).
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and the device
waits for serial clock input.
(5) When the serial clock is input, output the transmit data from the SOBn pin in synchronization with the
serial clock.
(6) When transmission of data of the transfer data length specified by the CBnCTL2 register is completed,
generate the reception complete interrupt request signal (INTCBnR) at the last edge of the serial clock
cycle, stop the serial clock input and transmit data output, and then clear the CBnTSF bit to 0.
(7) To continue transmission, repeat the above steps from (4) after the INTCBnR signal is generated.
(8) To end transmission, clear the CBnCTL0.CBnPWR and CBnCTL0.CBnTXE bits to 0.
Remark n = 0 to 4
R01UH0165EJ0700 Rev.7.00
Sep 22, 2011
Page 651 of 1113