UPD70F3793GC-UEU-AX Datasheet, PDF (654/1113 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-L Microcontrollers

V850ES/JG3-L
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
Figure 18-14. Single Transfer Mode Operation Timing (Slave Mode, Reception Mode)
CBnTSF bit
INTCBnR signal
SCKBn pin
SIBn pin
SIBn pin capture
timing
(1) (4)
(2)
(3)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(5)
(6) (7)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(8) (10)
(9)
(1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) =
external clock (SCKBn), and slave mode.
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A1H to the CBnCTL0 register, and select the reception mode and MSB first at the same time as
enabling the operation of the communication clock (fCCLK).
(4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and the
device waits for serial clock input.
(5) When the serial clock is input, capture the receive data of the SIBn pin in synchronization with the serial
clock.
(6) When reception of the data of transfer data length set by the CBnCTL2 register is completed, stop the
serial clock input and data capturing, generate the reception complete interrupt request signal
(INTCBnR) at the last edge of the serial clock, and clear the CBnTSF bit to 0.
(7) To continue reception, read the CBnRX register with the CBnCTL0.CBnSCE bit set to 1 after the
INTCBnR signal is generated, and wait for serial clock input.
(8) To end reception, clear the CBnSCE bit to 0.
(9) Read the CBnRX register.
(10) Clear the CBnCTL0.CBnPWR and CBnCTL0.CBnRXE bits to 0.
Remark n = 0 to 4
R01UH0165EJ0700 Rev.7.00
Sep 22, 2011
Page 654 of 1113