UPD70F3793GC-UEU-AX Datasheet, PDF (792/1113 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-L Microcontrollers

V850ES/JG3-L CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
21.2.1 Operation
If a non-maskable interrupt request signal is generated, the CPU performs the following processing and transfers
control to the handler routine.
<1> Saves the current PC to FEPC.
<2> Saves the current PSW to FEPSW.
<3> Writes exception code (0010H, 0020H) to the higher halfword (FECC) of ECR.
<4> Sets the PSW.NP and PSW.ID bits to 1 and clears the PSW.EP bit to 0.
<5> Sets the handler address (00000010H, 00000020H) corresponding to the non-maskable interrupt to the PC,
and transfers control.
The servicing of a non-maskable interrupt is shown below.
Figure 21-2. Non-Maskable Interrupt Servicing
INTC
acknowledged
CPU processing
NMI input
Non-maskable interrupt request
1
PSW.NP
0
FEPC
FEPSW
ECR.FECC
PSW.NP
PSW.EP
PSW.ID
PC
PC
PSW
0010H, 0020H
1
0
1
00000010H,
00000020H
Interrupt request held pending
Interrupt servicing
R01UH0165EJ0700 Rev.7.00
Sep 22, 2011
Page 792 of 1113