H8SX1668R Datasheet, PDF (85/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 2 CPU
Addressing Mode
Classifi-
cation
Instruction
Size
#xx Rn
@(d, @−ERn/
RnL.B/ @ERn+/
Rn.W/ @ERn−/
@aa:16/
@ERn @(d,ERn) ERn.L) @+ERn @aa:8 @aa:32 —
Arithmetic MULXS,
operations DIVXS
B/W S:4 SD
MULS, DIVS W/L S:4 SD
NEG
B
DD
D
D
D
D
D
W/L
DD
D
D
D
D
EXTU, EXTS W/L
DD
D
D
D
D
TAS
B
D
MAC*¹²
—
CLRMAC*¹² —
O
LDMAC*¹²
—
S
STMAC*¹²
—
D
Logic
AND, OR, XOR B
operations
B
S
D
D
DS
S
D
D
S
S
D
D
S
S
B
SD SD
SD SD
SD
W/L S
SD SD SD
SD SD
SD
NOT
B
DD
D
D
D
D
D
W/L
DD
D
D
D
D
Shift
SHLL, SHLR
B
W/L*⁵
B/W/L*⁷
DD
D
DD
D
D
D
D
D
D
D
D
D
SHAL, SHAR B
ROTL, ROTR _W/L
ROTXL,
ROTXR
DD
D
DD
D
D
D
D
D
D
D
D
Bit
manipu-
lation
BSET, BCLR, B
BNOT, BTST,
BSET/cc,
BCLR/cc
DD
D
D
BAND, BIAND, B
BOR, BIOR,
BXOR, BIXOR,
BLD, BILD,
BST, BIST,
BSTZ, BISTZ
DD
D
D
Rev. 2.00 Sep. 24, 2008 Page 53 of 1468
REJ09B0412-0200