H8SX1668R Datasheet, PDF (405/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 9 Bus Controller (BSC)
(10) RAS Down Mode and Software Standby Mode for DRAM Interface
When making a transition to software standby mode with the OPE bit in SBYCR set to 0 without
using the self-refresh mode, the transition should be made in RAS up mode (RCDM = 0). When
RAS down mode (RCDM = 1) is used, execute the SLEEP instruction after setting the RCDM bit
to 0. RAS down mode should be set again after recovery from software standby mode. For
SBYCR, see section 28, Power-Down Modes.
(11) RAS Down Mode and Clock Frequencies Setting for DRAM/SDRAM
Write access to SCKCR for setting the clock frequencies should be performed in RAS up mode
(RCDM = 0). When RAS down mode (RCDM = 1) is used, set the RCDM bit to 0 before writing
to SCKCR. RAS down mode should be set again after clock frequencies are set. For SCKCR, see
section 27, Clock Pulse Generator.
(12) Cluster Transfer to SDRAM Space
Cluster transfer mode is available for the SDRAM with CAS latency of 2. When the SDRAM is
used in cluster transfer mode, the SDRAM with CAS latency of 2 should be used. In cluster
transfer mode, the write-precharge output delay function by the TRWL bit is not available. The
TRWL bit must be cleared to 0.
Rev. 2.00 Sep. 24, 2008 Page 373 of 1468
REJ09B0412-0200