H8SX1668R Datasheet, PDF (148/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 6 Exception Handling
Table 6.3 Calculation Method of Exception Handling Vector Table Address
Exception Source
Calculation Method of Vector Table Address
Reset, CPU address error Vector table address = (vector table address offset)
Other than above
Vector table address = VBR + (vector table address offset)
[Legend]
VBR: Vector base register
Vector table address offset: See table 6.2.
6.3 Reset
A reset has priority over any other exception. When the RES pin goes low, all processing halts and
this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20
ms with the STBY pin driven high when the power is turned on. When operation is in progress,
hold the RES pin low for at least 20 states.
The chip can also be reset by the overflow that is generated in watchdog timer mode of the
watchdog timer. For details, see section 28, Power-Down Modes, and section 18, Watchdog Timer
(WDT).
A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules.
The interrupt control mode is 0 immediately after a reset.
6.3.1 Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, VBR is cleared to H'00000000, the T bit is cleared to 0 in EXR, and the I bits are
set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 6.1 and 6.2 show examples of the reset sequence.
Rev. 2.00 Sep. 24, 2008 Page 116 of 1468
REJ09B0412-0200