H8SX1668R Datasheet, PDF (772/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 14 16-Bit Timer Pulse Unit (TPU)
(2) Examples of Buffer Operation
(a) When TGR is an output compare register
Figure 14.16 shows an operation example in which PWM mode 1 has been designated for channel
0, and buffer operation has been designated for TGRA and TGRC. The settings used in this
example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at
compare match B.
As buffer operation has been set, when compare match A occurs, the output changes and the value
in buffer register TGRC is simultaneously transferred to timer general register TGRA. This
operation is repeated each time compare match A occurs.
For details on PWM modes, see section 14.4.5, PWM Modes.
TCNT value
TGRB_0
TGRA_0
H'0000
H'0200
TGRC_0 H'0200
Transfer
TGRA_0
H'0450
H'0200
H'0450
H'0520
H'0450
H'0520
Time
TIOCA
Figure 14.16 Example of Buffer Operation (1)
Rev. 2.00 Sep. 24, 2008 Page 740 of 1468
REJ09B0412-0200