H8SX1668R Datasheet, PDF (1004/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 20 USB Function Module (USB)
Initial
Bit
Bit Name Value R/W Description
4
SURSF
0
R/W Suspend/Resume Detection
This bit is set to 1 when the state changed from normal
to suspended state or vice versa. The corresponding
interrupt output is RESUME, USBINTN2, and
USBINTN3.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
3
CFDN
0
R/W End Point Information Load End
This bit is set to 1 when writing data in the endpoint
information register to the EPIR register ends (load
end). This module starts the USB operation after the
endpoint information is completely set.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
2
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
1
SETC
0
R/W Set_Configuration Command Detection
When the Set_Configuration command is detected, this
bit is set to 1.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
0
SETI
0
R/W Set_Interface Command Detection
When the Set_Interface command is detected, this bit
is set to 1.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
Rev. 2.00 Sep. 24, 2008 Page 972 of 1468
REJ09B0412-0200