H8SX1668R Datasheet, PDF (430/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 10 DMA Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
4
DARA4 0
R/W Destination Address Extended Repeat Area
3
DARA3 0
2
DARA2 0
1
DARA1 0
0
DARA0 0
R/W Specify the extended repeat area on the destination
R/W ^{address (DDAR). With the extended repeat area, the}
specified lower address bits are updated and the
R/W _{remaining upper address bits are fixed. The extended}
R/W ^{repeat area size is specified from four bytes to 128}
Mbytes in units of byte and a power of 2.
When the lower address is overflowed from the
extended repeat area by address update, the address
becomes the start address and the end address of the
area for address addition and subtraction, respectively.
When an overflow in the extended repeat area occurs
with the DARIE bit set to 1, an interrupt can be
requested. Table 10.3 shows the settings and areas of
the extended repeat area.
Rev. 2.00 Sep. 24, 2008 Page 398 of 1468
REJ09B0412-0200