H8SX1668R Datasheet, PDF (800/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 14 16-Bit Timer Pulse Unit (TPU)
14.10.3 Caution on Cycle Setting
When counter clearing by compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
f = ^Pφ
(N + 1)
f: Counter frequency
Pφ: Operating frequency
N: TGR set value
14.10.4 Conflict between TCNT Write and Clear Operations
If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed. Figure 14.47 shows the timing in this
case.
TCNT write cycle
T₁
T₂
Pφ
Address
TCNT address
Write
Counter clear
signal
TCNT
N
H'0000
Figure 14.47 Conflict between TCNT Write and Clear Operations
Rev. 2.00 Sep. 24, 2008 Page 768 of 1468
REJ09B0412-0200