H8SX1668R Datasheet, PDF (563/1504 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 11 EXDMA Controller (EXDMAC)
11.6 Operation in Cluster Transfer Mode
In cluster transfer mode, transfer is performed by the consecutive read and write operations of 1 to
32 bytes using the cluster buffer. A part of the cluster transfer mode function differs from the
ordinary transfer mode functions (normal transfer, repeat transfer, and block transfer modes).
11.6.1 Address Mode
(1) Cluster Transfer Dual Address Mode (AMS = 0)
In this mode, both the transfer source and destination addresses are specified for transfer in the
EXDMAC internal registers. The transfer source address is set in the source address register
(EDSAR), and the transfer destination address is set in the destination address register (EDDAR).
The transfer is processed by performing the consecutive read of a cluster-size from the transfer
source address and then the consecutive write of that data to the transfer destination address. One
data access size to 32 bytes can be specified as a cluster size. When one data access size is
specified as a cluster size, block transfer mode (dual address mode) is used.
The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another
bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for the last write cycle. The EDACK signal is not output.
Figure 11.53 shows the data flow in the cluster transfer mode (dual address mode), figure 11.54
shows an example of the timing in cluster transfer dual address mode, and figure 11.55 shows the
cluster transfer dual address mode operation.
LSI
Transfer source: External memory
EDSAR access
Read Read Read
Read
One cluster size
Consecutive
read
Cluster buffer
Transfer destination: External device
EDDAR acces
Write Write Write
Write
Consecutive
write
One cluster size
Figure 11.53 Data Flow in Cluster Transfer Dual Address Mode
Rev. 2.00 Sep. 24, 2008 Page 531 of 1468
REJ09B0412-0200